Semiconductor device and method of manufacturing the same

ABSTRACT

A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film ( 6 ) and a second interlayer insulating film ( 4 ) formed of a low dielectric-constant film on a substrate, forming via holes ( 9 ) by using a first resist pattern ( 1   a ) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern ( 1   b ) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating ( 2   b ) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern ( 1   b ).

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device and amethod of manufacturing the same, and particularly to a semiconductordevice having a damascene structure and a method of manufacturing thesame.

[0003] 2. Description of the Related Art

[0004] In connection with enhancement in the integration ofsemiconductor devices and reduction in chip size, miniaturization ofwires and multi-layered wiring have been recently promoted. As a methodof forming a multi-layered wiring structure is generally carried out aso-called damascene process in which Cu is embedded into via holes andwiring trench patterns at the same time and then surface flattening iscarried out by using CMP (Chemical Mechanical Polishing) method to formwires. With the damascene process described above, the density of thewiring pattern can be increased, however, a wiring delay problem wouldoccur due to the parasitic capacity between wiring patterns if thewiring patterns are close to each other. Therefore, it is an importantobject to reduce the wiring capacity for an improvement in wiring delay.

[0005] As a method to reduce the wiring capacity is considered a methodof using material having a lower dielectric constant as an interlayerinsulating film in place of a SiO₂-based insulating film which has beenhitherto used (See JP(A)-2000-77409, etc.). Here, a conventionaldamascene process using low dielectric constant film as an interlayerinsulating film will be described with reference to the accompanyingdrawings. FIGS. 23A to 25C are cross-sectional views showing a via-firstprocess corresponding to one type of conventional damascene process.

[0006] First, as shown in FIG. 23A, a first etching stop film 7preventing diffusion of Cu and serving as an etching stopper for viaholes, a first interlayer insulating film 6 of SiO₂, a second etchingstop film 5 serving as an etching stopper for wire trench patterns, asecond interlayer insulating film 4 serving as a low dielectric constantfilm and a cap insulating film 3 of SiO₂ are successively deposited on awire substrate 8 on which a lower layer wire of Cu or the like is formedby a well-known method. Further, a first antireflection coating (ARC:Anti Reflection Coating) 2 a and a photoresist are successively coated,and then subjected to light-exposure and development treatments to forma first resist pattern 1 a for formation of the via holes 9.

[0007] Subsequently, as shown in FIG. 23B, the first antireflectioncoating 2 a, the cap insulating film 3, the second interlayer insulatingfilm 4, the second etching stop film 5 and the first interlayerinsulating film 6 are successively etched with the first resist pattern1 a being used as a mask by using a well-known dry etching technique toform a via hole 9 penetrating through these films. Thereafter, bycarrying out an oxygen plasma ashing treatment and a wet treatment usingorganic peeling liquid, the first resist pattern 1 a and the firstantireflection coating 2 a are peeled off, stripped off or removed andthe residual materials of the dry etching are removed.

[0008] After the wet treatment using the organic peeling liquid, asshown in FIGS. 23C and 24A, a second antireflection coating 2 b and aphotoresist are successively coated, and then subjected tolight-exposure and development treatments to form a second resistpattern 1 b through which the wire trench patterns are etched (see FIG.24B). Thereafter, by using a well-known dry etching technique, thesecond antireflection coating 2 b, the cap insulating film 3 and thesecond interlayer insulating film 4 are successively etched to form wiretrench patterns 10. Thereafter, by using the oxygen plasma ashing andthe wet treatment using the organic peeling liquid, the second resistpattern 1 b and the second antireflection film 2 b are peeled off, andthe residual materials of the dry etching are removed (see FIGS. 24C,25A, 25B). A wiring material 11 of Cu or the like is embedded in thewire trench patterns 10 and the via holes 9 and the surface thereof isflattened by the CMP method to form a dual damascene structure.

[0009] Reference is made to the description at pages 5 to 7 and FIG. 1of the above JP(A)-2000-77409.

[0010] As described above, according to the via-first dual damasceneprocess, the via holes 9 are formed by using the first resist pattern 1a, and after the first resist pattern 1 a is peeled off, the secondresist pattern 1 b for etching the wire trench patterns 10 issubsequently formed. However, in the conventional method, after the wetpeeling process using the basic organic peeling liquid for peeling thefirst resist pattern 1 a and the first antireflection coating 2 a andbefore the coating of the second antireflection coating 2 b or theresist, no pre-treatment is carried out, or dehydrating bake (for about2 minutes at a temperature of about 150° C. to 250° C.) or thinnerpre-wetting is merely carried out as a pre-treatment by a coatingmachine.

[0011] The dehydrating bake and the thinner pre-wetting treatments aimto remove water adsorbed on the substrate, particularly the inner wallof the via holes 9, and they do not aim to remove materials disturbingthe chemical reactions in the resist such as basic materials, etc.(hereinafter referred to as reaction inhibiting materials). Therefore,there is a problem that the resolution of the second resist pattern 1 bis lowered by the reaction inhibiting materials. That is, the chemicalreactions are promoted by using acid catalyst occurring in the resistthrough the light exposure so that the resist is partially made to beeasily dissoluble by developing liquid, thereby forming a resistpattern. However, the reaction inhibiting materials infiltrating intothe interlayer insulating film exudes into the resist to deactivate theacid catalyst and thus suppress the chemical reactions in the resist, sothat the resist at a part of the wire trench patterns 10, particularlythe resist in the neighborhood of the via holes 9 is not sufficientlyremoved and thus remains there.

[0012] If the wiring trench patterns are subsequently etched under thestate that the resist remains at the portion to be originally removed,the wire trench patterns 10 get out of shape, or particularly when alarge part of the resist remains as shown in FIG. 24B, etching residuecalled as crown 15 as shown in FIG. 25A remains around the via holes 9.The crown 15 is not dissolved in the organic peeling liquid, and thus itremains until the wiring material 11 is embedded. Therefore, thereoccurs a problem that reliability of the completed wires is reduced.

[0013] This problem also occurs when SiO₂ is used for the interlayerinsulating film, and it occurs more remarkably when a low dielectricconstant film is used for the interlayer insulating film. Since the lowdielectric constant film is generally formed of coarse film, it isdesigned so that chemical solution such as organic peeling liquid,cleaning liquid, etc. is liable to infiltrate into the inside of thefilm and floating substances in air are liable to adhere to the film.Therefore, when antireflection coating or resist coated on the filmconcerned is baked, reaction inhibiting materials contained in thechemical solution exude gradually from the film concerned into theresist.

[0014] It is also known that, in addition to the chemical solution suchas organic peeling liquid, cleaning liquid, etc., specific elements inthe interlayer insulating film function as the reaction inhibitingmaterials. Therefore, if formation of the resist pattern is performedunder such a condition that the interlayer insulating film or theetching stop film is exposed to the inner wall of the via-hole or thewiring trench pattern formed therein, the same problem as mentioned inthe above occurs.

[0015] This problem occurs not only in the via-first dual damasceneprocess, but also in other damascene processes such as a dual hard maskprocess, trench-first dual damascene process, etc. or in anothersemiconductor process having a step of forming a next resist patternafter a wet treatment using organic peeling liquid, cleaning liquid orthe like or forming a resist pattern under such a condition that theinsulating film is exposed to the inner wall of the via-hole or thetrench pattern.

SUMMARY OF THE INVENTION

[0016] The present invention has been implemented in view of theforegoing problem, and has an object to provide a method ofmanufacturing a semiconductor device, which can surely remove reactioninhibiting materials inducing resolution failure of a resist pattern,suppress adhesion of the reaction inhibiting materials in air orsuppress the influence of the reaction inhibiting materials in theinterlayer insulating film, particularly to provide a semiconductordevice formed by using the damascene process and method of manufacturingthe same.

[0017] In order to attain the above object, according to the presentinvention, there is provided a semiconductor device manufacturing methodcomprising a step of conducting a wet treatment using organic peeling orstripping or removing liquid or cleaning liquid on a substrate having aninsulating film formed thereon and then forming a resist pattern on theinsulating film, characterized in that before a resist serving as theresist pattern or antireflection coating provided between the insulatingfilm and the resist is coated subsequently to the wet treatment, apre-treatment for removing reaction inhibiting materials which arecontained in the organic peeling or stripping or removing liquid or thecleaning liquid and inhibit the chemical reaction of the resist isconducted.

[0018] According to the present invention, there is also provided asemiconductor device manufacturing method comprising: at least a step ofsuccessively depositing at least a first interlayer insulating film anda second interlayer insulating film on a substrate on which a wiringpattern is formed; a step of forming a first resist pattern on thesecond interlayer insulating film and forming via holes by dry etchingusing the first resist pattern as a mask so that the via holes penetratethrough the first interlayer insulating film and the second interlayerinsulating film; a step of conducting at least one wet treatment of atreatment of removing etching residual materials with organic peelingliquid and a treatment of cleaning with cleaning liquid; a step offorming a second resist pattern on the second interlayer insulatingfilm; a step of etching the second interlayer insulating film by usingthe second resist pattern as a mask to form wiring trench patterns; anda step of embedding wiring material in the via holes and the wiringtrench patterns and polishing the surface of the wiring material thusembedded to thereby form a wiring pattern, characterized in that beforea resist serving as the second resist pattern or antireflection coatingprovided between the second insulating film and the resist is coatedsubsequently to the wet treatment, a pre-treatment for removing reactioninhibiting materials which are contained in the organic peeling liquidor the cleaning liquid and inhibit the chemical reaction of the resistis conducted.

[0019] According to the present invention, there is also provided asemiconductor device manufacturing method comprising: at least a step ofdepositing at least a first interlayer insulating film, a secondinterlayer insulating film and a mask member formed of inorganicmaterial; a step of forming a first resist pattern on the mask memberand etching the mask member by using the first resist pattern to form ahard mask; a step of conducting at least one wet treatment of atreatment for removing etching residual materials with organic peelingliquid and a treatment for cleaning with cleaning liquid; a step offorming a second resist pattern on the hard mask; a step of forming viaholes by using dry etching using the second resist pattern as a mask sothat the via holes penetrate through the first interlayer insulatingfilm and the second interlayer insulating film; a step of etching thesecond interlayer insulating film by using the hard mask to form wiringtrench patterns after the second resist pattern is removed; and a stepof embedding wire material into the via holes and the wiring trenchpatterns and polishing the surface of the wiring material to form awiring pattern, characterized in that before a resist serving as thesecond resist pattern or antireflection coating provided between thesecond insulating film and the resist is coated subsequently to the wettreatment, a pre-treatment for removing reaction inhibiting materialswhich are contained in the organic peeling liquid or the cleaning liquidand inhibit the chemical reaction of the resist is conducted.

[0020] In the present invention, the insulating film or at least one ofthe first interlayer insulating film and the second interlayerinsulating film may be formed of a low dielectric-constant film.

[0021] In the present invention, the reaction inhibiting materials maycomprise basic materials so that catalysis action of acid occurring inthe resist due to light exposure is inhibited by the basic materials,and the basic materials preferably contain amine.

[0022] In the present invention, it is preferable that at least one ofan annealing treatment, a UV treatment, a plasma treatment and anorganic solvent treatment is carried out as the pre-treatment, and asthe pre-treatment is carried out the UV treatment after the annealingtreatment.

[0023] In the present invention, the annealing treatment may comprise atreatment for conducting annealing at a predetermined temperature toeliminate the reaction inhibiting materials infiltrated into or adsorbedto the insulating film, the first interlayer insulating film or thesecond interlayer insulating film, the UV treatment may comprise atreatment for neutralizing the reaction inhibiting materials infiltratedinto or adsorbed to the insulating film, the first interlayer insulatingfilm or the second interlayer insulating film with oxygen or ozoneactivated by irradiation of UV light, and the plasma treatment maycomprise a treatment for etching the reaction inhibiting materialsinfiltrated into or adsorbed to the insulating film, the firstinterlayer insulating film or the second interlayer insulating film withplasma containing at least one of oxygen, nitrogen and ammonia.

[0024] In the present invention, it is preferable that the organicsolvent treatment uses organic solvent containing any one ofpolypyreneglycol monomethyl ether acetate, polypyreneglycol monomethylether, ethyl lactate, cyclohexanone and methyl ethyl ketone.

[0025] In the present invention, the organic solvent may contain acidicmaterial so that the reaction inhibiting materials infiltrated into oradsorbed to the insulating film, the first interlayer insulating film orthe second interlayer insulating film are neutralized by the acidicmaterial, or, the organic solvent may contain weakly basic material sothat the reaction inhibiting materials infiltrated into or adsorbed tothe insulating film, the first interlayer insulating film or the secondinterlayer insulating film are substituted into the weakly basicmaterials.

[0026] According to the present invention, there is provided asemiconductor device manufactured by the above methods, wherein at leastone of an annealing treatment and a UV treatment is used as thepre-treatment, and the device comprises the wiring pattern formed in thevia holes or the wiring trench patterns and having a side wall, and theinsulating film having a face layer portion contacting at least aportion of the side wall of the wring pattern and an inner portion otherthan the face layer portion, the face layer portion having a compositionratio or density which is different from that of the inner portion.

[0027] According to the present invention, there is provided asemiconductor device having a dual damascene wiring structure,comprising at least one of a via and a wire made of conductive materialhaving a side wall, and an interlayer insulating film having a facelayer portion contacting at least a portion of the side wall of the viaor the wire and an inner portion other than the face layer portion,wherein the interlayer insulating film contains Si and O as apredominant element and the face layer portion is lower in nitrogenconcentration than the inner portion, or the interlayer insulating filmhas a low dielectric constant and contains Si, O and H as a predominantelement and the face layer portion is higher in oxygen concentration andlower in hydrogen concentration than the inner portion, or theinterlayer insulating film has a low dielectric constant and containsSi, O, C and H as a predominant element and the face layer portion ishigher in oxygen concentration and lower in carbon and hydrogenconcentrations than the inner portion.

[0028] According to the present invention, there is provided asemiconductor device having a dual damascene wiring structure,comprising at least one of a via and a wire made of conductive materialhaving a side wall, and a barrier film or an etching stop film having aface layer portion contacting at least a portion of the side wall of thevia or the wire and an inner portion other than the face layer portion,wherein the banner film or the etching stop film contains Si, C, N and Has a predominant element and the face layer portion is higher in oxygenconcentration and lower in carbon, nitrogen and hydrogen concentrationsthan the inner portion, or the barrier film or the etching stop filmcontains Si, C and H as a predominant element and the face layer portionis higher in oxygen concentration and lower in carbon and hydrogenconcentrations than the inner portion.

[0029] According to the present invention, there is provided asemiconductor device having a dual damascene wiring structure,comprising at least one of a via and a wire made of conductive materialhaving a side wall, and a low dielectric constant interlayer insulatingfilm having a face layer portion contacting at least a portion of theside wall of the via or the wire and an inner portion other than theface layer portion, wherein the interlayer insulating film contains Si,O and H or alternatively Si, O, C and H as a predominant element and theface layer portion is higher in density than the inner portion, or,comprising at least one of a via and a wire made of conductive materialhaving a side wall, and a barrier film or an etching stop film having aface layer portion contacting at least a portion of the side wall of thevia or the wire and an inner portion other than the face layer portion,wherein the barrier film or the etching stop film contains Si, C, N andH or alternatively Si, C and H as a predominant element and the facelayer portion is higher in density than the inner portion.

[0030] According to the present invention, there is provided asemiconductor device having a dual damascene wiring structure,comprising at least one of a via and a wire made of conductive materialhaving a side wall, and a low dielectric constant interlayer insulatingfilm having a face layer portion contacting at least a portion of theside wall of the via or the wire and an inner portion other than theface layer portion, wherein the interlayer insulating film contains Si,O and H as a predominant element and the face layer portion is higher ina ratio of Si—O bond and lower in a ratio of Si—H bond than the innerportion, or the interlayer insulating film contains Si, O, C and H as apredominant element and the face layer portion is higher in a ratio ofSi—O bond and lower in a ratio of Si—CH₃ bond than the inner portion,or, comprising at least one of a via and a wire made of conductivematerial having a side wall, and a barrier film or an etching stop filmhaving a face layer portion contacting at least a portion of the sidewall of the via or the wire and an inner portion other than the facelayer portion, wherein the barrier film or the etching stop filmcontains Si, C, N and H or alternatively Si, C and H as a predominantelement and the face layer portion is lower in a ratio of Si—CH₃ bondthan the inner portion.

[0031] In the present invention, the thickness of the face layer portionis preferably set to 30 nm or less in order to suppress increase of thedielectric constant. The low dielectric constant interlayer insulatingfilm containing Si, O and H as a predominant element may be ladderhydrogenated siloxane, and L-Ox (registered trademark) may be used asthe ladder hydrogenated siloxane.

[0032] As described above, according to the present invention, theannealing treatment, the plasma treatment, the UV treatment, the organicsolvent treatment or the like may be conducted as the pre-treatment forforming the resist pattern, whereby the reaction inhibiting materialssuch as amine, etc. remaining in wafer, particularly in the lowdielectric-constant interlayer insulating film can be surely removed.Furthermore, a modified film having modified composition, density orbond state is formed by conducting the annealing treatment or the UVtreatment on a face layer of the insulating film, the barrier film orthe etching stop film confronting the via hole or the wiring trenchpattern formed therein, whereby adhesion of the reaction inhibitingmaterials in air to the film or influence of the reaction inhibitingmaterials in the insulating film can be suppressed. Therefore, thepresent invention can solve the problem that the resolution of a resistpattern is degraded in the process containing a step of forming theresist pattern subsequently to a wet treatment using organic peelingliquid or cleaning liquid which contains amine, etc. as in the case of adual damascene process such as a via-first process, a dual hard maskprocess, a trench-first process or the like, or a step of forming theresist pattern subsequently to formation of the via hole or the wiringtrench pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033]FIGS. 1A to 1C are cross-sectional views showing the procedure ofa via first process according to a first embodiment of the presentinvention;

[0034]FIGS. 2A to 2C are cross-sectional views showing the procedure ofthe via first process according to the first embodiment of the presentinvention;

[0035]FIGS. 3A to 3C are cross-sectional views showing the procedure ofthe via first process according to the first embodiment of the presentinvention;

[0036]FIG. 4 is a diagram showing the construction of a gas analysissystem to set the condition of an annealing treatment according to thefirst embodiment of the present invention;

[0037]FIGS. 5A and 5B are graphs showing analysis results achieved bythe gas analysis system;

[0038]FIGS. 6A and 6B are graphs showing gas analysis results achievedfor a sample using SiO₂ as an interlayer insulating film and a sampleusing a dielectric-constant film as an interlayer insulating film;

[0039]FIGS. 7A and 7B show SEM observation results achieved for thesample using SiO₂ as the interlayer insulating film and the sample usingthe dielectric-constant film as the interlayer insulating film;

[0040]FIG. 8 is a diagram showing the difference in effect of aminocomponents due to the difference in via pattern interval;

[0041]FIGS. 9A and 9B are graphs showing the effect of a WV treatmentaccording to the first embodiment of the present invention;

[0042]FIGS. 10A to 10C show the effect of an organic solvent treatmentaccording to the first embodiment of the present invention;

[0043]FIGS. 11A to 11C are cross-sectional views showing the procedureof a via first process according to a second embodiment of the presentinvention;

[0044]FIGS. 12A to 12C are cross-sectional views showing the procedureof the via first process according to the second embodiment of thepresent invention;

[0045]FIGS. 13A to 13C are cross-sectional views showing the procedureof the via first process according to the second embodiment of thepresent invention;

[0046]FIGS. 14A to 14C are cross-sectional views showing the procedureof a dual hard mask process according to a third embodiment of thepresent invention;

[0047]FIGS. 15A to 15C are cross-sectional views showing the procedureof the dual hard mask process according to the third embodiment of thepresent invention;

[0048]FIG. 16 is a cross-sectional view showing the procedure of thedual hard mask process according to the third embodiment of the presentinvention;

[0049]FIGS. 17A to 17C are cross-sectional views showing the procedureof a via first process according to a fourth embodiment of the presentinvention;

[0050]FIGS. 18A to 18C are cross-sectional views showing the procedureof the via first process according to the fourth embodiment of thepresent invention;

[0051]FIG. 19 is a cross-sectional view showing the procedure of the viafirst process according to the fourth embodiment of the presentinvention;

[0052]FIGS. 20A to 20C are cross-sectional views showing the procedureof a trench first process according to the fourth embodiment of thepresent invention;

[0053]FIGS. 21A to 21C are cross-sectional views showing the procedureof the trench first process according to the fourth embodiment of thepresent invention;

[0054] FIGS. 22 is a cross-sectional view showing the procedure of thetrench first process according to the fourth embodiment of the presentinvention;

[0055]FIGS. 23A to 23C are cross-sectional views showing the procedureof a conventional via first process;

[0056]FIGS. 24A to 24C are cross-sectional views showing the procedureof the conventional via fist process;

[0057]FIGS. 25A to 25C are cross-sectional views showing the procedureof the conventional via first process;

[0058]FIG. 26 is a diagram showing a method of extracting materialsinfiltrated into the interlayer insulating film;

[0059]FIGS. 27A and 27B show extraction results of the method of FIGS.25A to 25C; and

[0060]FIG. 28 is a diagram showing a mechanism for the resolutiondegradation of the resist pattern.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0061] In a case where PR step is carried out sequentially to a wettreatment step such as a wet peeling or stripping or removing step, acleaning step or the like, when antireflection coating or resist iscoated with no pre-treatment like a conventional damascene process,reaction inhibiting materials such as basic chemical materials or thelike infiltrated into a substrate invade through the antireflectioncoating into the resist. As a result, there occurs the problem that thechemical reaction of the resist due to light exposure is inhibited, andthe resist pattern suffers resolution failure.

[0062] Particularly, this problem frequently occurs in the case where alow dielectric-constant insulating film is used in place of siliconoxide. This is because the low dielectric-constant material is moreliable to accept the reaction inhibiting materials therein because thelow dielectric-constant material has a higher void density than thesilicon oxide film, so that the low dielectric-constant materialgradually exudes in the baking process of the antireflection coating orresist. Further, in a via-first process in which via holes arepreferentially processed, organic peeling or stripping or removingliquid used after the via hole etching infiltrates deeply into thesubstrate along the via holes.

[0063] Therefore, in order to solve the above problem, the followingtest has been carried out to identify the reaction inhibiting materialswhich cause degradation of the resolution of the resist pattern.

[0064] First, a via-formed sample 17 in which via holes 9 were formed bythe conventional method (see FIG. 23B) was prepared, and the via-formedsample 17 was put in a quartz cell 16 and heated at a temperature of300° C. as shown in FIG. 26. Thereafter, materials occurring due to theheating were extracted into pure water after the sample 17 was cooled,and the components were identified by capillary cataphoresis. The resultis shown in FIGS. 27A and 27B. As is apparent from FIGS. 27A and 27B, itis found that in the comparison between the analysis result of astandard sample having no via hole shown in FIG. 27A and the analysisresult of the via-formed sample 17 shown in FIG. 27B, the materialssurrounded by a broken line (amine A and amine B, hereinafter referredto as “amine components”) each have the peak at the same migration timeunder cataphoresis in capillary. The components determined here arecomponents of amine type organic peeling liquid. Accordingly, it isascertained that the components of amine type organic peeling liquidadheres to the surface of the substrate.

[0065] That is, in the via-first process, etching residual materials areremoved by using amine-based alkaline organic peeling or stripping orremoving liquid in the organic peeling or stripping or removing processcarried out after the via holes are etched. In this process, the organicpeeling liquid infiltrates into the first interlayer insulating film 6and the second interlayer insulating film, and it is not perfectlyremoved even in the subsequent cleaning step. Particularly, a lowdielectric-constant organic/inorganic interlayer insulating film has ahigher micro-void density, and the reaction inhibiting materialsinfiltrate into these micro voids. These reaction inhibiting materialsin the micro voids exude through the second antireflection coating 2 binto the resist when the second antireflection coating 2 b and theresist are baked.

[0066] A mechanism showing that the amine components induce theresolution failure of the resist pattern will be described withreference to FIG. 28.

[0067] First, acid generating agent (onium salt type acid generatingagent, diazomethane type acid generating agent, sulfonic ester type acidgenerating agent or the like) contained in a positive type resist isphotolyzed by light exposure and acid is generated. Protecting groupssuch as acetal groups having a dissolution inhibiting effect ondeveloping liquid are changed to hydroxyl groups by a deblockingreaction based on the acid catalyst, so that the polarity of the resistis changed and is liable to be dissolved in the developing liquid.Accordingly, when the basic amine components infiltrate into the resist,the acid catalyst is deactivated by neutralization and the deblockingreaction described above is inhibited. Such phenomenon is called“poisoning”

[0068] It is estimated that, as a result, the solubility of the resistmaterial into the developing liquid is lowered, the resist resolution islowered and the resist embedded in the via holes is partially left,thereby inducing degradation of the pattern resolution. Further, theresolution failure of the resist pattern likewise occurs due to theresidual materials of hydrofluoric acid hydrogen peroxide used in a Cuback surface cleaning step before PR.

[0069] The inventors of the present invention have found out that theabove poisoning is caused not only by the amine components but also inaccordance with the concentration of specific elements such as nitrogen,hydrogen, carbon and the like which constitute the insulating film suchas the interlayer insulating film or the etching stop film. If a nextresist pattern is formed under such a condition that the interlayerinsulating film or the etching stop film is exposed to the via-hole orthe wiring trench pattern formed therein, the reaction inhibitingmaterials in the insulating film act on the resist to cause the sameproblem as in the case of amine components.

[0070] Therefore, according to the present invention, an annealingtreatment, a plasma treatment, a UV treatment, an organic solventtreatment with organic solvent containing acidic or weakly basiccompound or the like is conducted as a pre-treatment for coating resistor antireflection coating to effectively remove the reaction inhibitingmaterials such as amine, hydrofluoric acid hydrogen peroxide, etc.remaining in the wet process, or the annealing treatment or the UVtreatment is conducted as a pre-treatment to form a modified layerhaving a modified composition, density or bond state on the face of theinsulating film exposed to the via hole or the wiring trench pattern atthe inner face thereof so as to suppress adhesion of the reactioninhibiting materials floating in air to the insulating film or suppressinfluence of the reaction inhibiting materials in the insulating film,thereby suppressing occurrence of poisoning and improving the resolutionfailure of the resist pattern.

[0071] The annealing treatment is carried out at a temperature of 150°C. to 450° C., preferably at a temperature of 200° C. to 450° C. tosurely eliminate the reaction inhibiting materials or form the modifiedlayer. When the annealing treatment is carried out, it is preferablycarried out under a pressure-reduced condition, under inert gasatmosphere of nitrogen, argon or the like or under hydrogen atmosphere.

[0072] In order to remove the reaction inhibiting materials attached inthe neighborhood of the surface, it is effective to wash out them withsolvent (thinner) before the antireflection coating is coated. Further,in order to remove the reaction inhibiting materials exuding up to theupper surface of the antireflection coating in the bake step after theantireflection coating is coated, a thinner treatment after theantireflection coating is coated is effective. The cleaning processusing organic solvent containing acidic material or organic solventcontaining weak basic material in place of the thinner treatmentdescribed above is more effective to remove the alkaline reactioninhibiting materials. In order to neutralize the reaction inhibitingmaterials, it is effective to contain acid in the antireflection coatingitself.

[0073] Further, the UV treatment is a method of removing the reactioninhibiting materials by oxygen or ozone activated by the irradiation ofthe UV light. The plasma treatment is a method of physically etching oroxidizing the exposed surface of the interlayer insulating film by usingplasma of gas such as oxygen, hydrogen, nitrogen, ammonia or the like.The UV treatment and the plasma treatment have not only an effect ofremoving the reaction inhibiting materials, but also an effect ofreforming the exposed substrate surface to improve wettability of theantireflection coating and the resist coated after the UV treatment orthe plasma treatment. It is preferable to carry out the UV treatment byusing a high pressure mercury lamp or excimer laser of wavelength of 100nm to 500 nm at an irradiation intensity of 50 mW/cm² or more.Especially, according to the UV treatment with use of oxygen, a modifiedlayer having a modified composition, density or bond state can be formedon the face of the insulating film exposed to the via hole or the wiringtrench pattern at the inner wall thereof so as to suppress the influenceof the reaction inhibiting materials in air or the insulating film.

[0074] Next, the specific procedure of the damascene process to whichthe above pre-treatments are applied will be described on the basis ofthe following examples. It is well known that amine is contained inorganic peeling liquid, however, it is a novel fact achieved from theknowledge of the inventors of the present invention that amine affectsthe resolution of the resist pattern and the concentration of theelements such as nitrogen, hydrogen, carbon, etc. contained in theinsulating film also functions as the reaction inhibiting materials inthe same manner as the case of amine.

EXAMPLES

[0075] Next, examples of the present invention will be describedhereunder with reference to the accompanying drawings to describe thepresent invention in more detail.

[0076] Both the amine contained in the chemical solution such as organicpeeling liquid, cleaning liquid, etc. and the composition of elementssuch as nitrogen, hydrogen, carbon, etc. contained in the insulatingfilm influence the poisoning phenomenon, however, details of thepre-treatment for a case of removing only the residual amine aredifferent from those of another case of suppressing adhesion of theamine in air or suppressing influence of the reaction inhibitingmaterials in the insulating film. For the purpose of simple explanation,the first to third examples focus on the method for effective removal ofthe residual amine, while the fourth example focuses on the method ofsuppressing adhesion of the amine in air and suppressing influence ofthe reaction inhibiting materials in the insulating film. In thefollowing examples, the dual damascene method is shown basically as toonly one wiring layer where the via and the wire are formedsimultaneously, however, it should be noted that the process may beconducted repeatedly to form a plurality of wiring layers.

Example 1

[0077] A first example of a semiconductor device and its manufacturingmethod to which the present invention relates will be described withreference to FIGS. 1A to 10C.

[0078]FIGS. 1A to 3C are cross-sectional views showing the procedure ofa via-first process of the first example, and as a matter of convenienceof drawing, it is illustrated as being divided into plural diagrams.FIG. 4 is a diagram showing the construction of a gas analysis system toset the condition of an annealing treatment. FIGS. 5A and 5B showanalysis results thereof. FIGS. 6A to 7B are diagrams showing thedifference between a case where SiO₂ is used as an interlayer insultingfilm and another case where a low dielectric-constant film is used as aninterlayer insulting film and FIG. 8 is a diagram showing the differencein effect of amine component due to the difference in via patterninterval. Further, FIGS. 9A and 9B are diagrams showing the effect of aUV treatment, and FIGS. 10A to 10C show the effect of an organic solventtreatment.

[0079] A via-first process according to this embodiment will bedescribed hereunder.

[0080] First, as shown in FIG. 1A, a lower layer wire (not shown) of Cuor the like is formed on a wiring substrate 8 by a well-known method,and then a first etching stop film 7, a first interlayer insulating film6 and a second etching stop film 5 are successively formed by using aCVD method, a plasma CVD method or the like so that each film has apredetermined film thickness. On the second etching stop film 5 isdeposited SiO₂, an organic low dielectric-constant film, an organicmaterial-contained silicon oxide film, an organic or inorganic porousfilm, L-Ox™, a fluorine-contained insulating film thereof or the like,thereby forming a second interlayer insulating film 4. Thereafter, a capinsulating film 3 is formed.

[0081] The first interlayer insulating film 6, the cap insulating film3, the first etching stop film 7 and the second etching stop film 5 maybe formed of any combination of materials so as to achieve a selectionratio of the etching, and the materials are properly selected from SiO₂,SiC, SiN, SiON, SiCN, etc. Further, when SiO₂ is used for the secondinterlayer insulating film 4, it is unnecessary to form the capinsulating film 3. However, when materials other than SiO₂ are used,there may occur a problem in CMP step of wires. In this case, it isrequired to form the cap insulating film 3.

[0082] Thereafter, a first antireflection coating 2 a for suppressingreflection of exposure light is deposited at a thickness of about 50 nm,a chemical amplification type or chemical sensitization type resist iscoated at a thickness of about 600 nm, and then the light exposure anddevelopment based on KrF photolithography is carried out to form a firstresist pattern 1 a.

[0083] Subsequently, as shown in FIG. 1B, the first antireflectioncoating 2 a, the cap insulating film 3, the second interlayer insulationfilm 4, the second etching stop film 5 and the first interlayerinsulating film 7 are successively etched to form via holes 9 so thatthe via holes 9 penetrate through these films. Thereafter, the resistpattern 1 a and the first antireflection coating 2 a are peeled off byoxygen plasma ashing and a wet treatment using organic peeling liquid,and the residual materials of the dry etching are removed.

[0084] According to the conventional technique, in the next resistpattern forming step, no pre-treatment is carried out or only thedehydration bake or the thinner pre-wet is carried out at a temperatureof 150° C. to 250° C. for about 2 minutes as a pre-treatment by acoating machine before a second antireflection coating 2 b is coated.However, as described above, the conventional technique has the problemthat the amine components contained in the organic peeling liquidinfiltrate into the first interlayer insulating film 6 and the secondinterlayer insulating film 4, particularly the interlayer insulatingfilm formed of the low dielectric-constant film, exude in the bakeprocess after the coating of the second antireflection film 2 b and theresist and then penetrate through the second antireflection film 2 binto the resist to thereby lower the resolution of the resist. In viewof the foregoing problem, this example is characterized in that thefollowing treatment is carried out as a pre-treatment to form the secondresist pattern 1 b.

[0085] Any method may be used for the pre-treatment insofar as reactioninhibiting materials such as amine components, etc. infiltrating intothe interlayer insulating film, the etching stop film and the capinsulating film can be surely removed by the method. For example, as thepre-treatment may be used an annealing treatment under predeterminedtemperature and time conditions, a plasma treatment for physicallyetching the first interlayer insulating film 6 and the second interlayerinsulating film 4 exposed to the inner wall of the via holes to removethe amine components, a UV treatment for neutralizing the aminecomponents by oxidizing agent such as oxygen, ozone or the like which isactivated by UV light, an organic solvent treatment for neutralizingamine or replacing amine into weak base with organic solvent containingacidic or weakly basic material or the like.

[0086] These methods have respective characteristics, and for examplethe annealing treatment is generally carried out in the semiconductorprocess and thus it can be easily adopted. However, it takes long timeto carry out the heating treatment, and the amine components existing inthe atmosphere may be absorbed by wafer again when the wafer is pickedup from an anneal furnace. In the plasma treatment, the UV treatment andthe organic solvent treatment, the treatment time is short. Particularlyin the plasma treatment and the UV treatment, the surface of thesubstrate is reformed to thereby improve the wettability of theantireflection coating and the resist coated subsequently. Accordingly,it is preferable that the treatment choice is properly determined on thebasis of the performance of devices to be required, the number ofmanufacturing steps, facilities being used, etc., and these treatmentsmay be used alone or in combination. The combination process of carryingout the UV treatment after the annealing treatment and before thecoating of the antireflection coating is particularly effective.

[0087] Here, a case where the annealing treatment is carried out as thepre-treatment will be described.

[0088] When the conditions such as the annealing temperature, theannealing time, etc. of the annealing treatment are set, the effect ofremoving the amine components is enhanced as the annealing treatment iscarried out at a higher temperature for a longer time. However, thehigh-temperature and long-time annealing treatment not only increasesthe number of manufacturing steps, but also causes diffusion of Cu(wiring material), etc., so that the device characteristic may bedeteriorated.

[0089] Therefore, in order to determine preferable annealing temperatureand time for the annealing treatment, samples having different annealconditions were prepared, and gas components eliminated from wafer wereanalyzed according to mass spectrometry using a gas analysis systemshown in FIG. 4 (TD-API-MS method). Specifically, wafer was put in aheating furnace with a gas collecting quartz cell put on a sample(via-formed wafer), and the sample was heated by an infrared heaterunder the state that high-purity Ar gas was supplied into the furnacewhile adjusting the flow rate of the Ar gas by a mass flow controller.Gas eliminated from the wafer was introduced into an API-MS apparatusand analyzed. The analysis result is shown in FIGS. 5A and 5B.

[0090]FIG. 5A is a graph showing the temperature increasing curve andthe detection intensity of the amine components when the sample isgradually (every about 10° C./minute) increased from the normaltemperature to 400°, and it is apparent from FIG. 5A that aminecomponents are gradually eliminated as the temperature increases. FIG.5B is a graph showing a case where the temperature is increased in ashort time from the normal temperature to 400° C. and then kept at 400°C., and it is apparent from FIG. 5B that most of amine components areeliminated within about 20 minutes from the start of the temperatureincrease, and no amine component is detected after 20 minutes.

[0091] As described above, the amine components can be surely removed byincreasing the temperature to about the temperature (400° C.) at whichamine is vaporized. Particularly, the amine components can beeffectively removed in a short time (about 20 minutes) by quicklyincreasing the temperature. Even when the sample is kept at 400° C.thereafter, no amine component is detected. Therefore, it is apparentthat the amine removing effect acts on not only the amine componentsattached onto the surface of the sample, but also the amine componentsinfiltrated in the interlayer insulating film.

[0092] The annealing temperature is not limited to 400° C. Even when theannealing temperature is less than 400° C., the amine components couldbe removed if a long annealing time is set. According to the experimentsof the inventors of this invention, it is discovered that the annealingtemperature is preferably set in the range from 150° C. to 450° C.Further, in order to suppress elimination of amine components in thebaking process of the antireflection coating and the resist, it ispreferable that the lower limit of the annealing temperature is set to200° C. (baking temperature) or more. The annealing treatment ispreferably conducted under a pressure-reduced condition, under inert gasatmosphere of nitrogen, argon or the like or under hydrogen atmospherein order to prevent oxidation of the substrate.

[0093] After the amine components in the first interlayer insulatingfilm 6 and the second interlayer insulating film 4 are removed by theannealing treatment, the second antireflection coating 2 b is coated ata thickness of about 50 nm and then baked as shown in FIG. 1C. At thistime, the antireflection coating 2 b is partially embedded in the viaholes 9.

[0094] Subsequently, as shown in FIG. 2A, a chemical amplification typeresist is coated at a thickness of about 600 nm on the antireflectioncoating 2 b and then baked, and then a second resist pattern 1 b to formwiring trench patterns is formed by the light exposure and developmentbased on KrF photolithography (see FIG. 2B). In the conventionalmanufacturing method, the amine components in the organic peeling liquidused to remove the residual materials of the via-hole etching filtrateinto the interlayer insulating film, and infiltrate into the resist inthe baking step of the antireflection coating and the resist, so thatthe pattern resolution of the resist is lowered. However, according tothis example, the annealing treatment is carried out to sufficientlyremove the amine components before the antireflection coating 2 b iscoated, so that the resolution of the resist pattern can be keptexcellently.

[0095] Thereafter, the second antireflection coating 2 b is removed bythe dry etching method as shown in FIG. 2C, and then the coverinsulating film 3 and the second interlayer insulating film 4 are etchedby using the second etching stop film 5 as an etching stopper as shownin FIG. 3A, thereby forming the wiring trench patterns 10.

[0096] Subsequently, as shown in FIG. 3B, the second resist pattern 1 band the second antireflection coating 2 b are peeled off by the oxygenplasma ashing and the wet treatment using the organic peeling liquid toremove the residual materials of the dry etching. Thereafter, the firstetching stop film 7 is removed, the wiring material 11 of Cu or the likeis embedded in the wiring trench patterns 10 thus achieved, and then thesurface of the wiring material 11 is polished and flattened by using theCMP method, thereby completing the dual damascene structure (see FIG.3C).

[0097] From SEM observation of the via-formed wafer thus formed, it hasbeen found that there was no pattern resolution failure and theannealing treatment of this example was effective to remove amine. Theeffect of this example is more remarkable when low dielectric-constantfilm is used as the second interlayer insulting film 4. In order toascertain the difference, API-MS analysis was carried out on a sampleusing low dielectric-constant film as the second interlayer insulatingfilm 4 and another sample using silicon oxide film as the secondinterlayer insulating film 4 by using the gas analysis system shown inFIG. 4. The analysis results are shown in FIGS. 6A and 6B, and the SEMobservation results are shown in FIGS. 7A and 7B.

[0098]FIG. 6A shows the detection amounts of amine A (left side) andamine B (right side) when the silicon oxide film is used as the secondinterlayer insulating film 4. The detection amounts of amine A and amineB are respectively equal to 6.1 ng/cm² and 63 ng/cm², which are not sohigh values. On the other hand, when the low dielectric-constant film isused as the second interlayer insulating film 4, the detection amountsof amine A and amine B are respectively equal to 44 ng/cm² and 220ng/cm², which are high values. This shows that the effect of amine isremarkable in the process using the low dielectric-constant film andthus the pre-treatment of this example is needed.

[0099] Checking this by using SEM photographs, it is apparent as shownin FIG. 7A that when the silicon oxide film is used as the secondinterlayer insulating film 4, the resist pattern is lost at the tipportions of the wiring trench patterns which are surrounded by a whitecircle, and no via hole (shown by a black area) is formed. On the otherhand, it is apparent as shown in FIG. 7B that when the lowdielectric-constant film is used as the second interlayer insulatingfilm 4, most of via holes 9 to be originally formed are missing, andthus the influence of the amine components is remarkable in the case ofthe low dielectric-constant film.

[0100] Such a trouble appears more remarkably at a portion where wiringpatterns are isolated from one another than at a portion where wiringpatterns are dense. That is, as shown in FIG. 8, the width of theinterlayer insulating film between the patterns is narrow at the patterndense portion (at the right side of FIG. 8), and the amount of aminecomponents infiltrating in the interlayer insulating film is small, sothat the pattern is little deformed at the pattern dense portion.However, the amine components exude from the surrounding large-areainterlayer insulating film at the pattern-isolated portion (at the leftside of FIG. 8), and thus the pattern is liable to be deformed.Accordingly, the annealing treatment of this example is more importantin semiconductor devices having a large number of isolated patterns.

[0101] In the foregoing description, the annealing treatment is used asan amine removing method. The plasma treatment, the UV treatment, theorganic solvent treatment, etc. may be used as other amine removingmethods as described above. Further, any combination of the annealingtreatment, the plasma treatment, the UV treatment, the organic solventtreatment, etc. may be adopted, and these treatments may be selectivelyadopted in accordance with the device figuration.

[0102] In order to confirm the effect of the UV treatment, both of asample which was subjected to the UV treatment (hereinafter referred toas “UV-treated sample”) and another sample which was subjected to notreatment (“non-treated sample”) were subjected to a heating treatmentby the gas analysis system shown in FIG. 4 to analyze eliminated gas.The analysis results are shown in FIGS. 9A and 9B. FIG. 9A shows themeasurement result of the intensity of the eliminated gas dischargedwhen the non-treated sample was heated, and FIG. 9B shows themeasurement result when the UV-treated sample was heated. Comparing boththe samples, the amount of amine components (hatched portion) dischargedin a low temperature area below 200° C. (temperature of coating andbaking the antireflection coating) is remarkably reduced from 10 ng/cm²to 1.8 ng/cm², and it shows that amine can be effectively removed by theUV treatment.

[0103] In order to remove the amine components attached in theneighborhood of the surface, washing using organic solvent such aspolypyreneglycol monomethyl ether acetate, polypyreneglycol monomethylether, ethyl lactate, cyclohexanone, methyl ethyl ketone or the like iseffective before the antireflection coating 2 b is coated. Further, inorder to remove the amine components exuding up to the upper surface ofthe antireflection coating 2 b through the baking step after the coatingof the antireflection coating 2 b, the organic solvent treatment afterthe coating of the antireflection coating 2 b is effective. By usingorganic solvent containing organic acid such as organic carboxylic acid,acetic acid or the like or inorganic acid such as hydrochloric acid orthe like in the organic solvent treatment, strongly basic aminecomponents can be neutralized and the effect can be more enhanced.Further, by washing with organic solvent containing weakly basicmaterial, the strongly basic amine components can be substituted intoweakly basic materials, and the action of the amine components can beinhibited. Still further, in order to neutralize the amine components,the effect can be more enhanced by containing acid in the antireflectioncoating itself.

[0104] In order to confirm the effects of the organic solvent treatmentand the organic solvent treatment with organic solvent containing acidicmaterial, a non-treated sample and samples which were treated withrespective organic solvents were prepared, and the number of resistresiduals, that is, the number of pattern defects were measured by SEMphotographs. FIGS. 10A to 10C show the results based on the SEMphotographs. From FIG. 10, it has been found that the non-treated sampleshown in FIG. 10A has five resist residuals as indicated by an arrowline (at which the overall area of each elliptic wiring trench patternis blacked) from the end portion, the sample subjected to the organicsolvent (thinner) treatment shown in FIG. 10B has four resist residualsand the sample subjected to the acidic organic solvent shown in FIG. 10Chas one resist residual, and thus the amine components can beeffectively removed by the organic solvent treatment.

[0105] In the foregoing description, the amine components serve as thereaction inhibiting materials lowering the resist resolution. However,the resolution is likewise lowered by residuals of hydrofluoric acidhydrogen peroxide used in the Cu back side cleaning step before PR. Theresiduals of hydrofluoric acid hydrogen peroxide can be effectivelyremoved by the annealing treatment, the plasma treatment, the UVtreatment or the organic solvent treatment or any combination thereof.

Example 2

[0106] A second example of the semiconductor device and itsmanufacturing method to which the present invention relates will bedescribed with reference to FIGS. 11A to 13C.

[0107]FIGS. 11A to 13C are cross-sectional views showing the procedureof a via-first process according to the second example, and as a matterof convenience of drawing, it is illustrated as being divided intoplural diagrams. This example is characterized in that theantireflection coating is perfectly filled in the via holes, and thestructure and the manufacturing method of the other portions are thesame as the first example.

[0108] First, as in the case of the first example, as shown in FIG. 11A,the lower-layer wire of Cu or the like is formed on the wiring substrate8 by a well known method, and then the first etching stop film 7, thefirst interlayer insulating film 6, the second etching stop film 5, thesecond interlayer insulating film 4 and the cap insulating film 3 aresuccessively formed by the CVD method, the plasma CVD method or thelike. Thereafter, the first antireflection coating 2 a of about 50 nm inthickness and a chemical amplification type resist of about 600 nm inthickness are coated on the cap insulating film 3, and the lightexposure and development based on the KrF photolithography are carriedout to form the first resist pattern 1 a.

[0109] Subsequently, as shown in FIG. 11B, the first antireflectioncoating 2 a, the cap insulating film 3, the second interlayer insulatingfilm 4, the second etching stop film 5 and the first interlayerinsulating film 7 are successively etched by the well-known dry etchingto form the via holes 9 penetrating through these films. Thereafter, theresist pattern 1 a and the first antireflection coating 2 a are peeledby the oxygen plasma ashing and the wet treatment using the organicpeeling liquid, and the residuals of the dry etching are removed.

[0110] Subsequently, as in the case of the first example describedabove, as the pre-treatment for formation of the second resist patternis carried out the anneal treatment under predetermined temperature andtime conditions, the plasma treatment for physically etching the innerwalls of the via holes 9 to remove the amine components, the UVtreatment for neutralizing the amine components with oxidizing agentsuch as oxygen, ozone or the like which is activated by UV light, theorganic solvent treatment for neutralizing amine or substituting amineinto weak alkaline with organic solvent containing acidic or weaklybasic material, or any combination of these treatments.

[0111] After the amine components in the interlayer insulating film areremoved by the pre-treatment, the second antireflection coating 2 b ofabout 50 nm is coated and baked as shown in FIG. 11C. At this time, inthis example, the via holes 9 are perfectly embedded with theantireflection coating 2 b in order to make uniform the thickness of theresist coated on the second antireflection coating 2 b so that thepattern resolution is enhanced and the second resist pattern 1 b can beeasily removed.

[0112] Subsequently, as shown in FIG. 12A, after the chemicalamplification type resist is coated on the antireflection coating 2 b ata thickness of about 600 nm and baked, the light exposure anddevelopment based on the KrF photolithography are carried out to formthe second resist pattern 1 b for formation of the wiring trenchpatterns (see FIG. 12B). At this time, as in the case of the firstexample, a predetermined pre-treatment is conducted before theantireflection coating 2 b is coated, and then a sufficient amount ofamine components are removed, so that the resolution of the resistpattern can be excellently kept.

[0113] Subsequently, the second antireflection coating 2 b, the capinsulating film 3 and the second interlayer insulating film 4 aresubjected to the dry etching in the first example described above.However, in the second example, the second antireflection coating 2 b isfilled in the via holes 9, and the etching speed of the secondantireflection coating 2 b is lower than that of each of the capinsulating film 3 and the second interlayer insulating film 4.Therefore, only the second antireflection coating 2 b is etched untilthe wire layer portion by anisotropic etch-back using oxygen plasma asshown in FIG. 12C. Subsequently, as shown in FIG. 13A, the coverinsulating film 3 and the second interlayer insulating film 4 are etchedby using the second etching stop film 5 as an etching stopper to formthe wiring trench patterns 10.

[0114] Subsequently, as shown in FIG. 13B, by the oxygen plasma ashingand the wet treatment using the organic peeling liquid, the secondresist pattern 1 b and the second antireflection coating 2 b are peeledoff and the residual materials of the dry etching are removed. After thefirst etching stop film 7 is removed, the wire material 11 of Cu or thelike is embedded in the wiring trench patterns 10 achieved, and it ispolished to flatten the surface by using the CMP method, therebycompleting the dual damascene structure (see FIG. 13C).

[0115] Checking the via-formed wafer thus formed on the basis of SEMphotographs, no pattern resolution failure was observed, and theannealing treatment of this example has been proved to be effective toremove amine. In this example, since the second antireflection coating 2b is filled in the via holes 9, the disadvantage that the resist remainsat the upper portion of the via holes 9 occurs hardly. Further, sincethe path extending from the inner walls of the via holes 9 through thesecond antireflection coating 2 b to the resist is long, the device ofthis example hardly suffer the influence of the amine components evenwhen the amine components remain somewhat in the interlayer insulatingfilm.

Example 3

[0116] Next, the semiconductor device and its manufacturing methodaccording to a third example of the present invention will be describedwith reference to FIGS. 14A to 16. FIGS. 14A to 16 are cross-sectionalviews showing the procedure of a dual hard mask process according to thethird example, and as a matter of convenience of drawing, it isillustrated as being divided into plural diagrams. This example ischaracterized in that the wiring trench pattern is formed by using ahard mask.

[0117] As in the case of the first and second examples, as shown in FIG.14A, the lower-layer wire of Cu or the like is formed on the wiringsubstrate 8 by a well-known method, and then the first etching stop film7, the first interlayer insulating film 6, the second etching stop film5 and the second interlayer insulating film 4 are successively formed byusing the CVD method, the plasma CVD method or the like. Subsequently,in this embodiment, a hard-mask film lower portion 13 and a hard maskfilm 12 which will serve an etching mask for the wiring trench patternsare deposited at a predetermined thickness on the second interlayerinsulating film 4 by using a predetermined material. Thereafter, thefirst antireflection coating 2 a of about 50 nm in thickness and thechemical amplification type resist of about 600 nm in thickness arecoated on the hard mask film 12, and then the light exposure anddevelopment based on the KrF photolithography are carried out to formthe first resist pattern 1 a.

[0118] Subsequently, as shown in FIG. 14B, the hard mask 12 is etchedwith the first resist pattern 1 a by well-known dry etching to form anopening to etch the wiring trench patterns. Thereafter, by using theoxygen plasma ashing and the wet treatment using the organic peelingliquid, the resist pattern 1 a and the antireflection coating 2 a arepeeled off and the residuals of the dry etching are removed.

[0119] Subsequently, as in the case of the first and second examples,one or any combination of the annealing treatment, the plasma treatment,the UV treatment and the organic solvent treatment is carried out as thepre-treatment to form the second resist pattern.

[0120] Subsequently, as shown in FIG. 14C, the second antireflectioncoating 2 b of about 50 nm in thickness and the chemical amplificationtype resist of about 600 nm in thickness are coated and baked, and thenthe light exposure and development based on the KrF photolithography arecarried out to form the second resist pattern 1 b to form the via holes.At this time, as in the case of the first and second examples, apredetermined pre-treatment is carried out before the coating of theantireflection coating 2 b to sufficiently remove the amine components,so that the resist pattern resolution can be excellently kept.

[0121] Subsequently, as shown in FIG. 15A, the second antireflectioncoating 2 b, the hard-mask film lower portion 13, the second interlayerinsulating film 4, the second etching stop film 5 and the firstinterlayer insulating film 6 are etched by using the second resistpattern 2 b as a mask through well-known dry etching to form the viaholes 9 penetrating through these films.

[0122] Thereafter, by the oxygen plasma ashing and the wet treatmentusing the organic peeling liquid, the second resist pattern 1 b and thesecond antireflection coating 2 b are peeled off and the residuals ofthe dry etching are removed as shown in FIG. 15B.

[0123] Subsequently, as shown in FIG. 15C, the hard-mask film lowerportion 13 and the second interlayer insulating film 4 are etched byusing the hard mask film 12 as a mask through the well-known dry etchingmethod to form the wiring trench patterns 10. Thereafter, the secondetching stop film 7 is removed, and the wiring material 11 of Cu or thelike is embedded in the wiring trench patterns 10 thus formed andpolished to flatten the surface thereof by using the CMP method, therebycompleting the dual damascene structure (see FIG. 16).

[0124] When all the interlayer insulating films are formed of organicfilms, the manufacturing process may be modified as follows. That is,the second antireflection coating 2 b, the hard-mask film lower portion13, the second interlayer insulating film 4 and the second etching stopfilm 5 may be etched by using the second resist pattern 1 b in the stepof FIG. 15B, and the hard-mask film lower portion 13 and the secondinterlayer insulating film 4 are etched by using the hard mask film 12in the step of FIG. 15C to form the wiring trench patterns 10. At thesame time, the first interlayer insulating film 6 is etched to form thevia holes 9 penetrating until the first etching stop film 7.

[0125] Upon observation of the via-formed wafer thus formed on the basisof SEM photographs, no pattern resolution failure was observed as in thecase of the first and second examples, and it has been proved that thepre-treatment of the third embodiment was effective to remove amine.Further, in this example, no via hole 9 is formed when the second resistpattern 1 b is formed, so that the unevenness of the substrate issuppressed and thus the precision of the second resist pattern can beenhanced. In addition, since the etching is carried out by using thehard mask, the processing of the wiring trench patterns is facilitated.

Example 4

[0126] A fourth example of the semiconductor device and itsmanufacturing method to which the present invention relates will bedescribed with reference to FIGS. 17A to 22.

[0127]FIGS. 17A to 19 are cross-sectional views showing the procedure ofa via-first process according to the fourth example, and FIGS. 20A to 22are cross-sectional views showing the procedure of a trench-firstprocess according to the fourth example. This example is characterizedin that a UV treatment or an annealing treatment or the combinationthereof is carried out as the pre-treatment so as to modify the qualitysuch as composition, density, bond state, etc. of a face layer portionof the insulating film exposed to the via hole or the wiring trenchpattern at the inner wall thereof.

[0128] First, as shown in FIG. 17A, the lower-layer wire 18 of Cu or thelike is formed on the wiring substrate 8 by a well known damasceneprocess. Then, as shown in FIG. 17B, the first etching stop film 7 suchas SiCN film having a thickness of about 30 to 100 nm, the firstinterlayer insulating film 6, the second etching stop film 5 and thesecond interlayer insulating film 4 are successively formed by the CVDmethod, the plasma CVD method or the like. Here, the second etching stopfilm 5 used as an etching stop film for forming the wiring trenchpattern is made of, for example, SiC or SiCN. If the wires can be stablyformed without dispersion by the etching process, the second etchingstop film 5 may be omitted. The first interlayer insulating film 6 andthe second interlayer insulating film 4 is, for example, a SiO₂ film, aninorganic low dielectric constant film L-Ox™ (ladder oxide) or aSiOC-based film. On the low dielectric constant film, a SiO₂ film may beformed as a cap insulating film 3 as shown in FIG. 17B.

[0129] Subsequently, as shown in FIG. 17C, a first resist pattern 1 a isformed by the well-known lithography technique, and the cap insulatingfilm 3, the second interlayer insulating film 4, the second etching stopfilm 5 and the first interlayer insulating film 7 are etched by thewell-known etching technique to form a via hole 9 penetrating them.

[0130] Thereafter, the first resist pattern 1 a used for the etching ofthe via hole 9 is removed with oxygen ashing or by using a plasma ofnitrogen-hydrogen mixture gas or helium-hydrogen mixture gas.Thereafter, washing is carried out by using amine-based organic peelingliquid, whereby the organic peeling liquid is adsorbed or absorbed bythe face layer portion of the films exposed to the via hole 9 especiallyin case of the films having lower dielectric constant. At this stage,although in the above examples 1 to 3 the annealing treatment, theplasma treatment, the UV treatment, the organic solvent treatment, orthe like is carried out, in this example a treatment of UV lightirradiation treatment, an annealing treatment at about 200 to 450° C. orthe combination thereof is carried out as shown in FIG. 18A in order tomodify the face layer portion of the insulating films exposed to the viahole 9 at the inner wall thereof.

[0131] As a result, the peeling liquid remaining in the via hole 9 andthe liquid taken up in the face layer portion of the interlayerinsulating films are removed, and a composition change, densification,bond state change, or the like of the face layer portion of theinsulating films exposed to the via hole 9 at the inner wall thereof isperformed. Here, although a modified film 19 is depicted in FIG. 18A inorder to expressively show such a modification of the insulating films,the interface between the modified film 19 and an inner portion of theinsulating film other than the face layer portion is not always clearlyformed. However, the effective thickness of the modified film 19 may beabout 30 nm or less. The above modification differs from a state of theinsulating films hardened and changed in composition by oxygen ashing orthe like for peeling the resist off. Property and effect of the modifiedfilm 19 is described later.

[0132] Subsequently, as shown in FIG. 18B, a second resist pattern 1 bis formed by the well-known lithography technique. Here, an organicantireflection coating may be formed under the second resist pattern 1b. It is preferable that the antireflection coating is formed so as notto completely fill the inside of the via hole 9 but to become lower thanthe height of wire, i.e. existing in the via hole 9 under the level ofthe second etching stop film 5. Thereafter, the cap insulating film 3and the second interlayer insulating film 4 are etched by the well-knownetching technique to form a wiring trench pattern 10.

[0133] In the pre-treatment of this example, since the modified film 19having large density is formed in the face layer portion of theinsulating film exposed to the via hole 9 at the inner wall thereof,adhesion of the reaction inhibiting materials such as amine floating inair to the insulating film can be suppressed, thereby preventingoccurrence of poisoning. Inventors of this invention have found outthat, in addition to amine, elements such as nitrogen, hydrogen, carbon,etc. also function as the reaction inhibiting materials. Therefore, thepoisoning based on the above elements also can be suppressedeffectively, because the concentration of nitrogen, hydrogen, carbon,etc. in the modified film 19 exposed to the via hole 9 at the inner wallthereof is lower than that in the inner portion of the insulating film.

[0134] Subsequently, as shown in FIG. 18C, the second resist pattern 1 bused for the wiring trench pattern etching is removed, and then thefirst etching stop film 7 at the bottom of the via hole 9 is removed byetching while the exposed second etching stop film 5 is also etched andremoved. Thereafter, wiring materials 11 formed of a banner film madeof, for example, Ta, TaN, Ti, TiN, or the laminated structure thereofand a conducting film made of Cu or the like is embedded in the wiringtrench pattern 10 and the via hole 9 simultaneously. Thereafter, asshown in FIG. 19, a portion of the wiring materials 11 which isunnecessary for forming the wire is removed by CMP method to form thewire of dual damascene structure.

[0135] As mentioned in the above, by conducting the UV treatment, theannealing treatment, or the combination thereof after the via hole 9 isformed, amine contained in the organic peeling liquid or washing liquidcan be surely removed, and by forming the modified film 19 having amodified composition, density or bond state at the face layer portion ofthe insulating film exposed to the via hole 9 at the inner wall thereof,adhesion of amine floating in air to the insulating film can besuppressed and influence of the reaction inhibiting materials in theinsulating film can be also suppressed.

[0136] Next, a process wherein the pre-treatment is applied to thetrench-first process is described in detail with reference to FIGS. 20Ato 22.

[0137] First, the first etching stop film 7, the first interlayerinsulating film 6, the second etching stop film 5, the second interlayerinsulating film 4 and the cap insulating film 3 are successively formedon the wiring substrate 8 having the lower-layer wire 18 in the samemanner as the above via-first process (See FIGS. 20A and 20B).

[0138] Subsequently, as shown in FIG. 20C, the first resist pattern 1 ais formed by the well-known lithography technique, and then an areawhere the wire is formed is etched to form the wiring trench pattern 10.

[0139] Subsequently, as shown in FIG. 21A, the first resist pattern 1 aused for the wiring trench pattern etching is removed by oxygen ashing,organic peeling liquid, etc., then the modified film 19 is formed at theface layer portion of the insulating films exposed to the wiring trenchpattern 10 at the inner wall thereof by the UV treatment, the annealingtreatment at about 200 to 450° C. or the combination thereof in the samemanner as the above process. A resist poisoning during the formation ofthe via hole resist pattern in the next step can be suppressed.

[0140] Subsequently, as shown in FIG. 21B, the second resist pattern 1 bis formed by the well-known lithography technique, and the via hole 9 isformed by the well-known etching technique. Thereafter, the wire isformed in the same manner as the via-first process (See FIGS. 21C and22).

[0141] As mentioned in the above, also in the trench-first process, byconducting the UV treatment, the annealing treatment, or the combinationthereof after the wiring trench pattern 10 is formed, amine contained inthe organic peeling liquid or washing liquid can be surely removed, andby forming the modified film 19 having a modified composition, densityor bond state at the face layer portion of the insulating film exposedto the wiring trench pattern 10 at the inner wall thereof, adhesion ofamine floating in air to the insulating film can be suppressed andinfluence of the reaction inhibiting materials in the insulating filmcan be also suppressed.

[0142] The property and effect of the modified film 19 where variousmaterials are used as the insulating film are described hereunder.

[0143] <SiO₂ Film>

[0144] When the SiO₂ film is used as the interlayer insulating filmexposed to the via hole 9 in the via-first process, the nitrogenconcentration of the SiO₂ film at the face layer portion thereof afterconducting the process flow (UV treatment or/and annealing treatment) isrelatively lower than that of the SiO₂ film at the inner portionthereof. Therefore, nitrogen elimination amount from the SiO₂ film atthe later step is reduced. There is a clear correlation between thenitrogen elimination amount and the via poisoning, where defects causedby the via poisoning increase as the nitrogen elimination amountincreases. Accordingly, it can be understood that the poisoning can besuppressed effectively by the pre-treatment of this example when theSiO₂ film is used as the interlayer insulating film.

[0145] <L-Ox™>

[0146] When the ladder oxide film, one of ladder hydrogenated siloxane,is used as the interlayer insulating film exposed to the wiring trenchpattern in the trench-first process, the density of the ladder oxidefilm at the face layer portion thereof after conducting the process flow(UV treatment or/and annealing treatment) is relatively greater thanthat of the ladder oxide film at the inner portion thereof. Therefore,amine amount taken up into the ladder oxide film at the organic peelingstep performed by using a chemical solution containing the amine as acomponent is reduced. On the other hand, in the conventional process,the amine amount taken up into the ladder oxide film is considerablyincreased, because the density of the ladder oxide film at the facelayer portion thereof is not made greater.

[0147] The amine amount taken up into the ladder oxide film can beeasily detected by TDS (Thermal Desorption Spectroscopy) prior to metalembedding step of the dual damascene process in terms of the nitrogenelimination amount or the gas elimination amount with nitrogen bond.With such a detection, it is confirmed that defects caused by the resistpoisoning increase as the amine uptake amount increases. If the UVtreatment time is prolonged, the density of the ladder oxide filmbecomes greater and accordingly the amount of amine taken up into theladder oxide film becomes smaller, whereby the defects can be greatlyreduced.

[0148] Furthermore, the composition of the ladder oxide film at the facelayer portion thereof after conducting the process flow (UV treatmentor/and annealing treatment) is relatively greater in oxygenconcentration and relatively smaller in hydrogen concentration thanthose of the ladder oxide film at the inner portion thereof.

[0149] Furthermore, as to the bond state, the ratio of Si—O bond in theladder oxide film is relatively higher at the face layer portion thereofthan at the inner portion thereof, while the ratio of Si—H bond in theladder oxide film is relatively lower at the face layer portion thereofthan at the inner portion thereof. Such a bond state can be easilydetected by FTIR method if the pre-treatment of the process flow iscarried out on an uniform film. Also in the actual structure, the bondstate can be determined by observation of cross-sectional SEM of thecleavage sample after relief etching with use of a buffered HF. That is,if the face layer portion of the ladder oxide film becomes to have theabove bond state, the etching rate thereof becomes significantly low sothat the face layer portion tends to be retained in etching, while theetching rate of the inner portion of the ladder oxide film remainsrather higher so that the inner portion tends to be removed in etching.Thus, the bond state can be easily detected. With this method, it wasdetermined that the thickness of the modified film 19 was 30 nm or lessand it was not increased when prolonging the duration of time of the UVtreatment or the annealing treatment. It was also determined that theoxygen concentration was highest at the face layer portion and graduallychanged toward the inside. There is a correlation between the bond stateand the film density, and the amount of amine taken up into the ladderoxide film tends to become lower as the ratio of Si—O bond increases andthe ratio of Si—H bond decreases. Accordingly, it can be understood thatthe poisoning can be suppressed effectively by the pre-treatment of thisexample when the ladder oxide film is used as the interlayer insulatingfilm.

[0150] In the above insulating film, the element concentration, thedensity and the bond state is gradually varied from the outer surface ofthe face layer portion toward the inner portion, that is, the quality ofthe face layer portion approaches to the quality of a portion of thefilm other than the face layer portion (the quality of the bulkinterlayer insulating film) toward the inner portion. The face layerportion has a dielectric constant higher than the bulk, and therefore ifthe face layer portion is thick the performance of the device is madelower. When a film having the structure where the quality of the film issteeply varied is used, the thickness of the high dielectric constantface layer portion should be thick. Therefore, if a film having thestructure where the quality of the film is gradually varied from theface layer portion to the inner portion is used, the effectivedielectric constant can be maintained lower as compared with thestructure where the quality of the film is steeply varied, so thatsufficient performance of the device can be achieved.

[0151] <SiOC Film>

[0152] When the SiOC film is used as a part of the interlayer insulatingfilm exposed to the via hole in the via-first process, the density ofthe SiOC film at the face layer portion thereof after conducting theprocess flow (UV treatment or/and annealing treatment) is relativelygreater than that of the SiOC film at the inner portion thereof.Therefore, the amount of amine taken up into the SiOC film is reduced.On the other hand, in the conventional process, the amount of aminetaken up into the SiOC film is considerably increased, because thedensity of the SiOC film at the face layer portion thereof is not madegreater.

[0153] As to the composition of the SiOC film after conducting theprocess flow (UV treatment or/and annealing treatment), the face layerportion is relatively higher in oxygen concentration and relativelylower in carbon and hydrogen concentrations than those of the SiOC filmat the inner portion thereof, and as such a tendency becomes moreremarkable the amount of amine taken up into the SiOC film becomeslower.

[0154] As to the bond state of the SiOC film, the face layer portion isrelatively higher in the ratio of Si—O bond and relatively lower in theratio of Si—CH₃ bond than those of the SiOC film at the inner portionthereof. There is a correlation between the bond state and the filmdensity, and the amount of amine taken up into the SiOC film tends tobecome lower as the ratio of Si—CH₃ bond decreases. Accordingly, it canbe understood that the poisoning can be suppressed effectively by thepre-treatment of this example when the SiOC film is used as theinterlayer insulating film.

[0155] In the above insulating film, the element concentration, thedensity and the bond state is gradually varied from the outer surface ofthe face layer portion toward the inner portion, that is, the quality ofthe face layer portion approaches to the quality of a portion of thefilm other than the face layer portion (the quality of the bulkinterlayer insulating film) toward the inner portion. The face layerportion has a dielectric constant higher than the bulk, and therefore ifthe face layer portion is thick the performance of the device is madelower. When a film having the structure where the quality of the film issteeply varied is used, the thickness of the high dielectric constantface layer portion should be thick. Therefore, if a film having thestructure where the quality of the film is gradually varied from theface layer portion to the inner portion is used, the effectivedielectric constant can be maintained lower as compared with thestructure where the quality of the film is steeply varied, so thatsufficient performance of the device can be achieved.

[0156] <SiCN Film>

[0157] When the SiCN film is used as the barrier film or the etchingstop film, the density of the SiCN film at the face layer portionthereof after conducting the process flow (UV treatment or/and annealingtreatment) is relatively greater than that of the SiCN film at the innerportion thereof. Therefore, the amount of amine taken up into the SiCNfilm is reduced. On the other hand, in the conventional process, theamount of amine taken up into the SiCN film is considerably increased,because the density of the SiCN film at the face layer portion thereofis not made greater.

[0158] As to the composition of the SiCN film after conducting theprocess flow (UV treatment or/and annealing treatment), the face layerportion is relatively higher in oxygen concentration and relativelylower in carbon, nitrogen and hydrogen concentrations than those of theSiCN film at the inner portion thereof, and as such a tendency becomesmore remarkable the amount of nitrogen eliminating from the face layerportion of the SiCN film becomes lower.

[0159] As to the bond state of the SiCN film, the face layer portion isrelatively higher in the ratio of Si—CH₃ bond than that of the SiCN filmat the inner portion thereof. There is a correlation between the bondstate and the film density, and the amount of amine taken up into theSiCN film tends to become lower as the ratio of Si—CH₃ bond decreases.Accordingly, it can be understood that the poisoning can be suppressedeffectively by the pre-treatment of this example when the SiCN film isused as the barrier film or the etching stop film.

[0160] In the above insulating film, the element concentration, thedensity and the bond state is gradually varied from the outer surface ofthe face layer portion toward the inner portion, that is, the quality ofthe face layer portion approaches to the quality of a portion of thefilm other than the face layer portion (the quality of the bulkinterlayer insulating film) toward the inner portion. The face layerportion has a dielectric constant higher than the bulk, and therefore ifthe face layer portion is thick the performance of the device is madelower. When a film having the structure where the quality of the film issteeply varied is used, the thickness of the high dielectric constantface layer portion should be thick. Therefore, if a film having thestructure where the quality of the film is gradually varied from theface layer portion to the inner portion is used, the effectivedielectric constant can be maintained lower as compared with thestructure where the quality of the film is steeply varied, so thatsufficient performance of the device can be achieved.

[0161] <SiC Film>

[0162] When the SiC film is used as the barrier film or the etching stopfilm, the density of the SiC film at the face layer portion thereofafter conducting the process flow (UV treatment or/and annealingtreatment) is relatively greater than that of the SiC film at the innerportion thereof. Therefore, the amount of amine taken up into the SiCfilm is reduced. On the other hand, in the conventional process, theamount of amine taken up into the SiC film is considerably increased,because the density of the SiC film at the face layer portion thereof isnot made greater.

[0163] As to the composition of the SiC film after conducting theprocess flow (UV treatment+annealing treatment), the face layer portionis relatively higher in oxygen concentration and relatively lower incarbon and hydrogen concentrations than those of the SiC film at theinner portion thereof, and as such a tendency becomes more remarkablethe amount of amine taken up into the face layer portion of the SiC filmbecomes lower. There is a correlation between the bond state and thefilm density, and the amount of amine taken up into the SiC film tendsto become lower as the ratio of Si—CH₃ bond decreases. Accordingly, itcan be understood that the poisoning can be suppressed effectively bythe pre-treatment of this example when the SiC film is used as thebarrier film or the etching stop film.

[0164] In the above insulating film, the element concentration, thedensity and the bond state is gradually varied from the outer surface ofthe face layer portion toward the inner portion, that is, the quality ofthe face layer portion approaches to the quality of a portion of thefilm other than the face layer portion (the quality of the bulkinterlayer insulating film) toward the inner portion. The face layerportion has a dielectric constant higher than the bulk, and therefore ifthe face layer portion is thick the performance of the device is madelower. When a film having the structure where the quality of the film issteeply varied is used, the thickness of the high dielectric constantface layer portion should be thick. Therefore, if a film having thestructure where the quality of the film is gradually varied from theface layer portion to the inner portion is used, the effectivedielectric constant can be maintained lower as compared with thestructure where the quality of the film is steeply varied, so thatsufficient performance of the device can be achieved.

[0165] In the above examples, the annealing treatment, the plasmatreatment, the UV treatment, the organic solvent treatment, etc. of thepresent invention are applied to the dual damascene process such as thevia-first process, the dual hard mask process or the trench-firstprocess, however, the present invention is not limited to the aboveexamples. For example, the present invention may be applied to anysemiconductor process containing a step of forming a resist patternsubsequently to the wet treatment using organic peeling liquid orwashing liquid containing basic materials such as amine components,hydrofluoric acid hydrogen peroxide or the like, or a step of forming aresist pattern subsequently to the patterning of the insulating film.

[0166] As described above, according to the semiconductor device and itsmanufacturing method of the present invention, the following advantagescan be achieved.

[0167] A first advantage of the present invention resides in that in theprocess containing the step of forming the resist pattern subsequentlyto the wet treatment using the organic peeling liquid or washing liquidcontaining amine or the like as in the case of the dual damasceneprocess such as the via-first process, the dual hard mask process, thetrench-first process or the like, or the step of forming the resistpattern subsequently to formation of the via hole or the wiring trenchpattern, the problem of the degradation in the resist pattern resolutioncan be solved.

[0168] This is because the reaction inhibiting materials such as amine,etc. remaining in the wafer, particularly in the low dielectric-constantinterlayer insulating film can be surely removed by performing thetreatment such as the annealing treatment, the plasma treatment, the UVtreatment, the organic solvent treatment or the like as thepre-treatment to form the resist pattern. In addition, by conducting theUV treatment or the annealing treatment, the modified film having amodified quality (composition, density, bond state, etc.) exposed to thevia hole or the wiring trench pattern at the face layer portion of theinsulating film, to thereby suppress adhesion of amine floating in airand suppress influence of the reaction inhibiting materials, i.e.specific elements in the insulating film.

[0169] A second advantage of the present invention resides in that thecoating of the antireflection coating, etc. can be facilitated and theprocessing precision of the resist pattern can be enhanced.

[0170] This is because the surface state can be reformed by the plasmatreatment or the UV treatment, so that the wettability of theantireflection coating and the resist can be improved.

[0171] As described above, in the conventional dual damascene processusing the conventional low dielectric constant film, no stable resistprocessing shape cannot be achieved due to the reaction inhibitingmaterials such as amine or the like. However, by performing thepre-treatment of the present invention, stable resist resolution can beachieved, and it can contribute to enhancement in yield.

What is claimed is:
 1. A semiconductor device manufacturing methodcomprising a step of conducting a wet treatment using organic peelingliquid or cleaning liquid on a substrate having an insulating filmformed thereon and then forming a resist pattern on the insulating film,characterized in that before a resist serving as the resist pattern orantireflection coating provided between the insulating film and theresist is coated subsequently to the wet treatment, a pre-treatment forremoving reaction inhibiting materials which are contained in theorganic peeling liquid or the cleaning liquid and inhibit the chemicalreaction of the resist is conducted.
 2. The semiconductor devicemanufacturing method as claimed in claim 1, wherein the insulating filmcomprises a low dielectric-constant film.
 3. A semiconductor devicemanufacturing method comprising: at least a step of successivelydepositing at least a first interlayer insulating film and a secondinterlayer insulating film on a substrate on which a wiring pattern isformed; a step of forming a first resist pattern on the secondinterlayer insulating film and forming via holes by dry etching usingthe first resist pattern as a mask so that the via holes penetratethrough the first interlayer insulating film and the second interlayerinsulating film; a step of conducting at least one wet treatment of atreatment of removing etching residual materials with organic peelingliquid and a treatment of cleaning with cleaning liquid; a step offorming a second resist pattern on the second interlayer insulatingfilm; a step of etching the second interlayer insulating film by usingthe second resist pattern as a mask to form wiring trench patterns; anda step of embedding wiring material in the via holes and the wiringtrench patterns and polishing the surface of the wiring material thusembedded to thereby form a wiring pattern, characterized in that beforea resist serving as the second resist pattern or antireflection coatingprovided between the second insulating film and the resist is coatedsubsequently to the wet treatment, a pre-treatment for removing reactioninhibiting materials which are contained in the organic peeling liquidor the cleaning liquid and inhibit the chemical reaction of the resistis conducted.
 4. A semiconductor device manufacturing method comprising:at least a step of depositing at least a first interlayer insulatingfilm, a second interlayer insulating film and a mask member formed ofinorganic material; a step of forming a first resist pattern on the maskmember and etching the mask member by using the first resist pattern toform a hard mask; a step of conducting at least one wet treatment of atreatment for removing etching residual materials with organic peelingliquid and a treatment for cleaning with cleaning liquid; a step offorming a second resist pattern on the hard mask; a step of forming viaholes by using dry etching using the second resist pattern as a mask sothat the via holes penetrate through the first interlayer insulatingfilm and the second interlayer insulating film; a step of etching thesecond interlayer insulating film by using the hard mask to form wiringtrench patterns after the second resist pattern is removed; and a stepof embedding wire material into the via holes and the wiring trenchpatterns and polishing the surface of the wiring material to form awiring pattern, characterized in that before a resist serving as thesecond resist pattern or antireflection coating provided between thesecond insulating film and the resist is coated subsequently to the wettreatment, a pre-treatment for removing reaction inhibiting materialswhich are contained in the organic peeling liquid or the cleaning liquidand inhibit the chemical reaction of the resist is conducted.
 5. Thesemiconductor device manufacturing method as claimed in claim 3 or 4,wherein at least one of the first interlayer insulating film and thesecond interlayer insulating film is formed of a low dielectric-constantfilm.
 6. The semiconductor device manufacturing method as claimed in anyone of claims 1, 3 and 4, wherein the reaction inhibiting materialscomprise basic materials so that catalysis action of acid occurring inthe resist due to light exposure is inhibited by the basic materials. 7.The semiconductor device manufacturing method as claimed in claim 6,wherein the basic materials contain amine.
 8. The semiconductor devicemanufacturing method as claimed in any one of claims 1, 3 or 4, whereinat least one of an annealing treatment, a UV treatment, a plasmatreatment and an organic solvent treatment is carried out as thepre-treatment.
 9. The semiconductor device manufacturing method asclaimed in claim 8, wherein as the pre-treatment is carried out the UVtreatment after the annealing treatment.
 10. The semiconductor devicemanufacturing method as claimed in claim 8, wherein the annealingtreatment comprises a treatment for conducting annealing at apredetermined temperature to eliminate the reaction inhibiting materialsinfiltrated into or adsorbed to the insulating film, the firstinterlayer insulating film or the second interlayer insulating film. 11.The semiconductor device manufacturing method as claimed in claim 10,wherein the annealing treatment is carried out in a temperature rangefrom 150° C. to 450° C.
 12. The semiconductor device manufacturingmethod as claimed in claim 11, wherein the annealing treatment iscarried out at a temperature higher than the bake temperature of theantireflection coating or the resist.
 13. The semiconductor devicemanufacturing method as claimed in claim 10, wherein the annealingtreatment is carried out under a pressure-reduced condition, undernitrogen gas atmosphere, under inert gas atmosphere, or under hydrogenatmosphere.
 14. The semiconductor device manufacturing method as claimedin claim 8, wherein the UV treatment comprises a treatment forneutralizing the reaction inhibiting materials infiltrated into oradsorbed to the insulating film, the first interlayer insulating film orthe second interlayer insulating film with oxygen or ozone activated byirradiation of UV light.
 15. The semiconductor device manufacturingmethod as claimed in claim 8, wherein the plasma treatment comprises atreatment for etching the reaction inhibiting materials infiltrated intoor adsorbed to the insulating film, the first interlayer insulating filmor the second interlayer insulating film with plasma containing at leastone of oxygen, nitrogen and ammonia.
 16. The semiconductor devicemanufacturing method as claimed in claim 8, wherein the organic solventtreatment uses organic solvent containing any one of polypyreneglycolmonomethyl ether acetate, polypyreneglycol monomethyl ether, ethyllactate, cyclohexanone and methyl ethyl ketone.
 17. The semiconductordevice manufacturing method as claimed in claim 16, wherein the organicsolvent contains acidic material so that the reaction inhibitingmaterials infiltrated into or adsorbed to the insulating film, the firstinterlayer insulating film or the second interlayer insulating film areneutralized by the acidic material.
 18. The semiconductor devicemanufacturing method as claimed in claim 16, wherein the organic solventcontains weakly basic material so that the reaction inhibiting materialsinfiltrated into or adsorbed to the insulating film, the firstinterlayer insulating film or the second interlayer insulating film aresubstituted into the weakly basic materials.
 19. A semiconductor devicemanufactured by the method as claimed in m)any one of claims 1, 3 and 4,wherein at least one of an annealing treatment and a UV treatment isused as the pre-treatment, and the device comprises the wiring patternformed in the via holes or the wiring trench patterns and having a sidewall, and the insulating film having a face layer portion contacting atleast a portion of the side wall of the wiring pattern and an innerportion other than the face layer portion, the face layer portion havinga composition ratio or density which is different from that of the innerportion.
 20. A semiconductor device having a dual damascene wiringstructure, comprising at least one of a via and a wire made ofconductive material having a side wall, and an interlayer insulatingfilm having a face layer portion contacting at least a portion of theside wall of the via or the wire and an inner portion other than theface layer portion, wherein the interlayer insulating film contains Siand O as a predominant element and the face layer portion is lower innitrogen concentration than the inner portion.
 21. A semiconductordevice having a dual damascene wiring structure, comprising at least oneof a via and a wire made of conductive material having a side wall, anda low dielectric constant interlayer insulating film having a face layerportion contacting at least a portion of the side wall of the via or thewire and an inner portion other than the face layer portion, wherein theinterlayer insulating film contains Si, O and H as a predominant elementand the face layer portion is higher in oxygen concentration and lowerin hydrogen concentration than the inner portion.
 22. The semiconductordevice having a dual damascene wiring structure as claimed in claim 21,wherein the face layer portion has a distribution in concentration inwhich the oxygen concentration is highest and the hydrogen concentrationis lowest at the outer surface thereof and the oxygen concentration isgradually reduced and the hydrogen concentration is gradually increasedtoward the inner portion to approach to those of the inner portion. 23.A semiconductor device having a dual damascene wiring structure,comprising at least one of a via and a wire made of conductive materialhaving a side wall, and a low dielectric constant interlayer insulatingfilm having a face layer portion contacting at least a portion of theside wall of the via or the wire and an inner portion other than theface layer portion, wherein the interlayer insulating film contains Si,O, C and H as a predominant element and the face layer portion is higherin oxygen concentration and lower in carbon and hydrogen concentrationsthan the inner portion.
 24. The semiconductor device having a dualdamascene wiring structure as claimed in claim 23, wherein the facelayer portion has a distribution in concentration in which the oxygenconcentration is highest and the carbon and hydrogen concentrations arelowest at the outer surface thereof and the oxygen concentration isgradually reduced and the carbon and hydrogen concentrations aregradually increased toward the inner portion to approach to those of theinner portion.
 25. A semiconductor device having a dual damascene wiringstructure, comprising at least one of a via and a wire made ofconductive material having a side wall, and a barrier film or an etchingstop film having a face layer portion contacting at least a portion ofthe side wall of the via or the wire and an inner portion other than theface layer portion, wherein the barrier film or the etching stop filmcontains Si, C, N and H as a predominant element and the face layerportion is higher in oxygen concentration and lower in carbon, nitrogenand hydrogen concentrations than the inner portion.
 26. Thesemiconductor device having a dual damascene wiring structure as claimedin claim 25, wherein the face layer portion has a distribution inconcentration in which the oxygen concentration is highest and thecarbon, nitrogen and hydrogen concentrations are lowest at the outersurface thereof and the oxygen concentration is gradually reduced andthe carbon, nitrogen and hydrogen concentrations are gradually increasedtoward the inner portion to approach to those of the inner portion. 27.A semiconductor device having a dual damascene wiring structure,comprising at least one of a via and a wire made of conductive materialhaving a side wall, and a barrier film or an etching stop film having aface layer portion contacting at least a portion of the side wall of thevia or the wire and an inner portion other than the face layer portion,wherein the barrier film or the etching stop film contains Si, C and Has a predominant element and the face layer portion is higher in oxygenconcentration and lower in carbon and hydrogen concentrations than theinner portion.
 28. The semiconductor device having a dual damascenewiring structure as claimed in claim 27, wherein the face layer portionhas a distribution in concentration in which the oxygen concentration ishighest and the carbon and hydrogen concentrations are lowest at theouter surface thereof and the oxygen concentration is gradually reducedand the carbon and hydrogen concentrations are gradually increasedtoward the inner portion to approach to those of the inner portion. 29.A semiconductor device having a dual damascene wiring structure,comprising at least one of a via and a wire made of conductive materialhaving a side wall, and a low dielectric constant interlayer insulatingfilm having a face layer portion contacting at least a portion of theside wall of the via or the wire and an inner portion other than theface layer portion, wherein the interlayer insulating film contains Si,O and H or alternatively Si, O, C and H as a predominant element and theface layer portion is higher in density than the inner portion.
 30. Asemiconductor device having a dual damascene wiring structure,comprising at least one of a via and a wire made of conductive materialhaving a side wall, and a barrier film or an etching stop film having aface layer portion contacting at least a portion of the side wall of thevia or the wire and an inner portion other than the face layer portion,wherein the barrier film or the etching stop film contains Si, C, N andH or alternatively Si, C and H as a predominant element and the facelayer portion is higher in density than the inner portion.
 31. Thesemiconductor device having a dual damascene wiring structure as claimedin claim 29 or 30, wherein the face layer portion has a distribution indensity in which the density is highest at the outer surface thereof andgradually reduced toward the inner portion to approach to that of theinner portion.
 32. A semiconductor device having a dual damascene wiringstructure, comprising at least one of a via and a wire made ofconductive material having a side wall, and a low dielectric constantinterlayer insulating film having a face layer portion contacting atleast a portion of the side wall of the via or the wire and an innerportion other than the face layer portion, wherein the interlayerinsulating film contains Si, O and H as a predominant element and theface layer portion is higher in a ratio of Si—O bond and lower in aratio of Si—H bond than the inner portion.
 33. The semiconductor devicehaving a dual damascene wiring structure as claimed in claim 32, whereinthe face layer portion has a distribution in bond ratio in which theSi—O bond ratio is highest and the Si—H bond ratio is lowest at theouter surface thereof and the Si—O bond ratio is gradually reduced andthe Si—H bond ratio is gradually increased toward the inner portion toapproach to those of the inner portion.
 34. A semiconductor devicehaving a dual damascene wiring structure, comprising at least one of avia and a wire made of conductive material having a side wall, and a lowdielectric constant interlayer insulating film having a face layerportion contacting at least a portion of the side wall of the via or thewire and an inner portion other than the face layer portion, wherein theinterlayer insulating film contains Si, O, C and H as a predominantelement and the face layer portion is higher in a ratio of Si—O bond andlower in a ratio of Si—CH₃ bond than the inner portion.
 35. Thesemiconductor device having a dual damascene wiring structure as claimedin claim 34, wherein the face layer portion has a distribution in bondratio in which the Si—O bond ratio is highest and the Si—CH₃ bond ratiois lowest at the outer surface thereof and the Si—O bond ratio isgradually reduced and the Si—CH₃ bond ratio is gradually increasedtoward the inner portion to approach to those of the inner portion. 36.A semiconductor device having a dual damascene wiring structure,comprising at least one of a via and a wire made of conductive materialhaving a side wall, and a barrier film or an etching stop film having aface layer portion contacting at least a portion of the side wall of thevia or the wire and an inner portion other than the face layer portion,wherein the barrier film or the etching stop film contains Si, C, N andH or alternatively Si, C and H as a predominant element and the facelayer portion is lower in a ratio of Si—CH₃ bond than the inner portion.37. The semiconductor device having a dual damascene wiring structure asclaimed in claim 36, wherein the face layer portion has a distributionin bond ratio in which a Si—O bond ratio is highest and the Si—CH₃ bondratio is lowest at the outer surface thereof and the Si—O bond ratio isgradually reduced and the Si—CH₃ bond ratio is gradually increasedtoward the inner portion to approach to those of the inner portion. 38.The semiconductor device having a dual damascene wiring structure asclaimed in any one of claims 20 to 30 and 32 to 37, wherein thethickness of the face layer portion is substantially 30 nm or less. 39.The semiconductor device having a dual damascene wiring structure asclaimed in any one of claims 21, 22, 29, 32 and 33, wherein the lowdielectric constant interlayer insulating film containing Si, O and H asa predominant element is ladder hydrogenated siloxane.
 40. Thesemiconductor device having a dual damascene wiring structure as claimedin claim 39, wherein L-Ox (registered trademark) is used as the ladderhydrogenated siloxane.